Advanced Research in VLSI and Parallel Systems: Proceedings by Thomas Knight, John Savage

By Thomas Knight, John Savage

The layout of hugely built-in or large-scale structures contains a suite of interrelated disciplines, together with circuits and units, layout automation, VLSI structure, software program structures, and thought. winning learn in any of those disciplines more and more will depend on an realizing of the opposite parts. This convention the 14th in a sequence that has been held at Caltech, MIT, UNC Chapel Hill, Stanford, and UC Santa Cruz, seeks to motivate interplay between researchers in all disciplines; that relate to hugely built-in platforms. Thomas Knight is affiliate Professor within the division of electric Engineering and laptop technological know-how on the Massachusetts Institute of expertise. John Savage is Professor within the division of desktop technological know-how at Brown collage. Topics coated: Circuits and units. Innovative electric circuits, optical computing, computerized semiconductor production, wafer-scale structures. layout Automation. Synthesis and silicon compilation, structure and routing, research and simulation, novel layout equipment, architectural layout aid, layout for try. VLSI structure. hugely parallel architectures, specialpurpose VLSI chips and platforms, novel small-scale structures, 1/0 and secondary garage, packaging, and fault tolerance. software program platforms. Architecturedriven programming versions, parallel languages, compiling for concurrency, working structures, synchronization. 'Theory. Parallel algorithms, VLSI thought, format and wireability research, 1/0 complexity, interconnection networks, reliability.

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For our example, since A = 1 causes no implication, we again choose a primary input B and assign B ~ 1 to provide a faulty signa l. Th en, A = 1 and B = I imply H = D. O nce the faul ty signal has been provided, the objective is to propagate a D or a D one level of gate closer to a primary out put than before. For our example, to propagate the val ue D on H to P we assign C = I, which is followed by the assignmen t E = O. At this point, C = 1 a nd E = 0 imply J = 1 and L = O. Continuing the assignment and implication.

DF*(X, h) ,X dh ( Hence, the fault h s-a-I is detected if and only if x , = 0 a nd x , = x, = 1. 3. The output is F(X) = x, + X, X , = x, + X , . 3. F can be expressed as a function F* of X and 1J: F*(X,h ) = x , + hx" where h(X) = x, , Th us, dF*(X, h) _ _ dh = x, Ell(x ,+x,) Logic Testing 30 The set of a ll tests tha t detect the fault Iz s-a- I is defined by Boolean exp ression - . dF*(X, Iz) Iz(X)' dlz _ =xtx ,x, = 0. This mean s that no test patterns exist for the fault Iz s-a-I ; tha t is, the fault h s-a- l is redun dant.

DF*(X, h) ,X dh ( Hence, the fault h s-a-I is detected if and only if x , = 0 a nd x , = x, = 1. 3. The output is F(X) = x, + X, X , = x, + X , . 3. F can be expressed as a function F* of X and 1J: F*(X,h ) = x , + hx" where h(X) = x, , Th us, dF*(X, h) _ _ dh = x, Ell(x ,+x,) Logic Testing 30 The set of a ll tests tha t detect the fault Iz s-a- I is defined by Boolean exp ression - . dF*(X, Iz) Iz(X)' dlz _ =xtx ,x, = 0. This mean s that no test patterns exist for the fault Iz s-a-I ; tha t is, the fault h s-a- l is redun dant.

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